Triple-threshold static power minimization technique in high-level synthesis using 90nm MTCMOS technology

As CMOS System-on-Chips approach the limits of power dissipation, static power has become dominant in a circuit’s total power dissipation. The static power is increasing exponentially as technology nodes shrink and is projected to exceed the dynamic power within the near future. Techniques that use the multi-threshold CMOS (MTCMOS) technology have been developed to reduce static power effectively. In this thesis, a novel triple-threshold static power minimization technique in high-level synthesis has been developed using the 90nm MTCMOS technology. Using static timing analysis, the optimal partitioning of gates with three different threshold voltages is determined via iterative analysis. The proposed triple-threshold technique has been applied to optimize several benchmark circuits, and the results show an average saving in static power close to 90% compared to un-optimized LVT designs. For all designs tested, the triple-threshold technique has produced designs with lower static power compared to a dual-threshold technique.