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Displaying 1 - 3 of 3
Triple-threshold static power minimization technique in high-level synthesis using 90nm MTCMOS technology
Author: Chen, Harry I-An
Date created: 2007
Evaluation and acceleration of spiking neural networks using FPGAs
Author: Panchapakesan, Sathish
Date created: 2021-11-29
An intermediate representation for transforming and optimizing the microarchitecture of application accelerators
Author: Sharifian, Amirali
Date created: 2020-07-27

Date created

Resource type

  • Thesis (2)

Collection

  • Engineering Science Theses (2)
  • Computing Science Theses (1)

Scholarly level

  • Graduate student (Masters) (1)
  • Graduate student (PhD) (1)

Author

  • Chen, Harry I-An (1)
  • Panchapakesan, Sathish (1)
  • Sharifian, Amirali (1)

Thesis Advisor

  • Fang, Zhenman (1)
  • Li, Jian (1)
  • Shriraman, Arrvindh (1)

Peer reviewed?

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Keywords

  • (-) High-level synthesis (3)
  • Integrated circuits -- Design and construction (1)
  • Static power reduction (1)
  • Spiking neural networks (1)
  • Multi-threshold (1)
  • Metal oxide semiconductors (1)
  • Machine Learning (1)
  • Low power (1)
  • Image classification (1)
  • Accelerator design (1)
  • Hardware acceleration (1)
  • FPGA (1)
  • Electric Leakage Prevention (1)
  • Digital integrated circuits (1)
  • Digital CMOS VLSI (1)
  • Configurable architecture (1)
  • Complementary -- Design and construction (1)
  • Triple-threshold (1)

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