An analytical model describing the performance of application-specific networks-on-chip on field-programmable gate arrays

Modern Field-Programmable Gate Arrays (FPGAs) are now used to implement complex Systems-on-Chip (SoCs) and more recently Networks-on-Chip (NoCs). NoCs consist of computing nodes that are connected via switches or routers to a network of point-to-point links, which define its topology. Appropriate topology choices for Application-Specific Integrated Circuits (ASICs) have been investigated, but due to an FPGA's fixed interconnect fabric, these conclusions are not necessarily applicable. Our research investigates how a commercial FPGA's fixed interconnect and CAD flow constrain the performance of NoCs based on a set of design parameters. We develop an analytical model that predicts the performance for both homogeneous and heterogeneous NoCs with a geometric mean error of 4.68% for Xilinx Virtex 2 Pro, Virtex 4, Virtex 5, and Virtex 6 FPGAs, and with a geometric mean error of 5.12% for Altera Stratix III and Stratix IV FPGAs.