VHDL implementation of a security co-processor

Tradeoffs of speed vs. area that are inherent in the design of a security coprocessor are explored. Encryption, decryption, and key generation engines for AES in Cipher Block Chaining and Electronic Code Book modes were developed using VHDL. Two designs are discussed. The "space-optimised" design required 1454 FPGA CLB slices for the Cipher implementation (401 6 for the complete design) and produced a round delay of - 16.75 ns. The throughput in CBC mode was 636.82 Mbps (depending on the FPGA utilized), which is greater than various published prior works. The Multi-Session Pipelined approach followed a novel architecture that required 13675 CLB slices total and produced a round delay of - 20 ns. The Multi-Session Pipelined AES design can obtain an aggregate throughput of - 6.40 Gbps and is capable of operating in CBC mode. The 1 Ox speedup over the "space-optimised" design required 3.4~ the total number of FPGA CLB slices.