Low-voltage single-phase clocked quasi-adiabatic pass-gate logic family for low-power submicron VLSI CMOS applications

As the growing complexity of mobile electronic applications leads to prohibitively high chip power demands, the energy efficiency of the integrated circuit devices will become more significant. Energy recovering circuitry based on adiabatic principles is a relatively new technique used to implement low energy dissipating circuits. By recycling the charge stored at capacitive nodes in the circuit, adiabatic logic families can achieve very low energy dissipation. This thesis presents a novel low-voltage Quasi-Adiabatic Pass-Gate (QAPG) logic family using a single power clock in 90nm CMOS technology. A comparative analysis is performed where circuits are constructed using previously proposed low-power single-phase clocked adiabatic logic and QAPG logic. Simulations demonstrate that the new logic family is suitable for low voltage operation down to 0.25V and down to the 32nm CMOS technology node. QAPG dissipates between eleven and forty percent of the total energy consumed by the previously proposed adiabatic logic families.