At-speed scan insertion and automatic test pattern generation of integrated circuits with fault-grading and speed-grading

With the growing complexity of today's integrated circuit designs, engineers have abandoned the use of pure functional test vectors wherever possible, and adopted various DFT solutions to make their designs more test-friendly. The most common DFT approach for digital designs is scan insertion and automatic test pattern generation (ATPG). ATPG is performed based on fault models associated with the design or gates within the design. Traditionally, the most popular model is the stuck-at model. However, as transistor size continues to shrink, new defect mechanisms start to appear that affect the speed of the design, and so can no longer be properly modelled by this model. Consequently, a new fault model called transition-delay fault models is created to allow ATPG to detect at-speed defects. Another model called path-delay fault model is also created for speed-gradinglbinning and I10 timing characterization on scan-inserted designs. As part of an ongoing DFT development for PMC-Sierra Inc., a suite of automation flows have been implemented to perform AC-Scan ATPG. This includes transition-delay ATPG with DC top-up ATPG for delay defect detection, path-delay ATPG for speed-gradinglbinning and I10 timing characterization, and AC-scan ATPG for RAM interfaces with multi-load algorithm.