Queue scheduler verification

This paper presents the complete verification process of Queue Scheduler. Queue Scheduler is an ASIC function block within PMC-Sierra's PM7354 SIUNI DUPLEX GE, a low cost ATM-to-Ethernet interworking chip for IP DSLAM. It is responsible for fairly scheduling traffic from up to 600 queues, going to up to two destination interfaces. It uses a fair queue scheduling algorithm, programmable for different applications. It is vitally important to verify Queue Scheduler's functional correctness thoroughly, in order to minimize the risk of doing a revision to reduce the overall development cost and to maintain time to market. This paper starts by detailing Queue Scheduler's design specification. After explaining the verification flow, it gives a detailed description of its testbench and testbench components. Next, it discusses the verification test points extracted from the design specification, and the resulting testcases. Finally, it presents the verification results.