Modeling Leakage in Sub-Micron CMOS Technologies

As CMOS technology scaling continues, subthreshold leakage current increases dramatically. A significant percentage of the total chip power is due to leakage, also known as static power. Accurately estimating static power in early stages of design is an important step for developing power efficient products. Leakage current is an important segment of total supply current (IDDQ), which is used as a means to identify defective chips. ID^^ value is determined by the sum of leakage currents of those transistors that can leak. Setting ID^^ value too high or low will result in excessive shipment of defective chips or yield loss because of rejecting good parts, respectively. The goal of this work is to investigate and model leakage mechanisms in submicron CMOS technology using SPICE circuit simulators. The main focus of this research will be subthreshold and reverse-bias p-n junction band-to-band leakage mechanisms and the effect of transistor parameters on them.