Phase noise analysis of a 0.18um CMOS fractional-N PLL for 802.11 a/b/g/n applications

In integrated CMOS 802.11 a/b/g/n direct conversion transceivers a key performance characteristic is the RMS value of RF clock phase noise at offsets between 1kHz and 20MHz. Phase noise analysis concepts related to fractional-N PLLs are presented and an optimization exercise determining PLL characteristics for a O.18pm CMOS fractional-N PLL in an 802.11 a/b/g/n RF frequency generation application is described. For fractional-N PLLs, modelling fractional-N phase noise effects and optimizing PLL characteristics to mitigate fractional-N effects is a major part of the PLL implementation process. Other major phase noise sources such as VCO noise must also be considered in optimizing PLL characteristics; considerations for other noise sources are discussed. Matlab is used to model fractional-N phase noise effects and to model overall PLL phase noise performance in the frequency domain. PLL characteristics are optimized with consideration for RMS phase noise at the PLL output and with consideration for PLL stability. Analysis is also performed to investigate the effect of variations in IC characteristics on PLL performance.