Design of Hardware Accelerators with Configurable Pipeline

In today’s world, people are widely using technology to make their lives more comfortable and better. The development of semiconductors technology is making Integrated Circuits(IC) smaller and smaller in size, thus allowing IC designer to include more and more functionalities in their products. This development of technology has allowed a large diffusion of semiconductor devices in all aspects of human life, leading to the concept of “embedded” computation, described as the practice of including the small processor devices in all spaces of our world, from our houses, to our cars, to even “wearable electronics” that we carry around as we move. In particular, floating point computation (FP) is a feature of computers that, at the price of significant additional hardware complexity and sometimes at the price of result accuracy, provides a much larger range of usable numbers, thus significantly enhancing the flexibility and usability of our computation. The additional hardware complexity imposed by FP units imposed a relevant price in Silicon Area (making the IC more expensive) and especially in terms of power consumption. In turn, energy consumption is a very severe issue in semiconductor technologies: first, it causes unreliability of the IC technology. Secondly, IC energy consumption leads to greenhouse gas emission. Finally, many IC systems are battery operated and high consumption may jeopardize the system usability and/or user experience. One very significant category of embedded processors is that of embedded sensors. Embedded sensors produce relevant quantities of raw data that needs to be adequately classified in order to provide significant information, and Machine Learning is often applied as a strategy for sensor data classification.This MENG project aims at exploring design strategies for low-power FP computation. In the following, we will introduce the design of a hardware FPU unit whose sub-blocks can be programmed to change dynamically the computational speed with the change in the voltage. This enables the FPU to adapt their consumption to the requirement of the environment, offering high performance (and high consumption) whenever needed by the environment, but adapting to low power, low speed mode whenever intensive processing is not necessary.