Design verification and performance analysis of Serial AXI Links in Broadcom System-on-Chip

Design verification is an essential step in the development of any product. Also referred to as qualification testing, design verification ensures that the product as designed is the same as the product as intended. In this project, design verification and performance analysis of Thin Advanced Extensible Interface Links (T-AXI) is conducted on a Broadcom’s SoC (System on Chip). T-AXI is a Broadcom’s proprietary bus that interfaces all the subsystems on the System-onchip (SoC) to the system memory. Test cases are developed to verify the functionality of the T-AXI and performance verification is implemented using scenarios derived from real world examples. A Field Programmable Gate Array (FPGA) is used to emulate the SoC design and C programming is used to write the test cases. The test results verify the T-AXI functionality and the performance analysis supports the theoretical calculations.