Developing electrostatic discharge (ESD) protection devices has traditionally relied on fabricating test chips during early stages of the integrated circuit design and subsequently testing the devices for optimization. However, in deep-submicron (DSM) CMOS technologies, fabricating test chips are unfeasible due to the cost and timing constraints. As a result, using 2-D device simulations to predict the failure point and to optimize ESD protection devices are becoming the preferred approach. Shallow trench isolation (STI) diodes available in DSM CMOS technologies have been widely used for ESD protection in high-speed mixed-signal and RF applications. In this thesis, 0.13 µm CMOS STI diodes have been calibrated and simulated using SEQUOIA Device Designer and the results allow to accurately predict the failure point and to optimize diode geometries for high-speed mixed-signal and RF applications. The proposed methodology can also be used in practice to aid the design of ESD protection in future deep submicron CMOS technologies.
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Thesis advisor: Syrzycki, Marek
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