Over the past few decades, the advancement in the deep-submicron CMOS process technology has dramatically improved the performance and functionality of modern System-on-Chips (SoC). However, as the complexity and operational speed of today’s SoCs increase, characterizing the timing performance of SoCs is becoming more challenging. Embedded measuring techniques for system characterization are therefore becoming necessities. A Time-to-Digital Converter (TDC) is a device that has been widely used for on-chip time measurements due to its excellent reliability and precision. However, accurate TDCs are few and most implementations are challenging, especially for the time resolution of 10ps and below. In this thesis, a new single-stage Vernier Time-to-Digital Converter (VTDC) has been implemented using 0.13μm IBM CMOS technology, and analyzed using HSPICE simulator in Cadence Analog Design Environment. The single-stage VTDC presented in this work utilizes a dynamic-logic phase detector and a Time Difference Amplifier (TDA). The zero dead-zone characteristic of dynamic-logic phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. At the same time, the constant gain TDA further improves the VTDC’s resolution by pre-amplifying the input time intervals. The developed single-stage VTDC with TDA has demonstrated a linear measurement characteristic for an input dynamic range from 0 to 100ps with a 2.5ps time resolution.
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Thesis advisor: Syrzycki, Marek
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