Analysis and design of a low-power low-noise CMOS phase-locked loop

Resource type
Thesis type
(Thesis) M.A.Sc.
Date created
Author: Zhang, Cheng
This thesis covers the analysis, design and simulation of a low-power low-noise CMOS Phase-Locked Loop (PLL). Starting with the PLL basics, this thesis discussed the PLL loop dynamics and behavioral modeling. In this thesis, the detailed design and implementation of individual building blocks of the low-power low-noise PLL have been presented. In order to improve the PLL performance, several novel architectural solutions has been proposed. To reduce the effect of blind-zone and extend the detection range of Phase Frequency Detector (PFD), we proposed the Delayed-Input-Edge PFD (DIE-PFD) and the Delayed-Input-Pulse PFD (DIP-PFD) with improved performance. We also proposed a NMOS-switch high-swing cascode charge pump that significantly reduces the output current mismatches. Voltage Controlled Oscillator (VCO) consumes the most power and dominates the noise in the PLL. A differential ring VCO with 550MHz to 950MHz tuning range has been designed, with the power consumption of the VCO is 2.5mW and the phase noise -105.2dBc/Hz at 1MHz frequency offset. Finally, the entire PLL system has been simulated to observe the overall performance. With input reference clock frequency equal 50MHz, the PLL is able to produce an 800MHz output frequency with locking time 400ns. The power consumption of the PLL system is 2.6mW and the phase noise at 1MHz frequency offset is -119dBc/Hz. The designs are implemented using IBM 0.13µm CMOS technology.
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Scholarly level
Supervisor or Senior Supervisor
Thesis advisor: Syrzycki, Marek
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