An improved data streaming model for synthetic system-on-chip benchmark circuit generation

Field Programmable Gate Array (FPGA) researchers aim to improve the quality of the Computer-Aided Design (CAD) tools used to map designs onto FPGAs and evaluate different possible architectures. To test new architectures and CAD tools, researchers need to use benchmark circuits representative of realistic applications, which are not freely available. Therefore, researchers have considered randomly-generated benchmark circuits that can model the complexities of real systems. We use the existing Benchmark Circuit Generator (BCGEN), which generates circuits with System-on-Chip (SoCs) architectures. While BCGEN provides a good framework for circuit generation, the existing dataflow communication patterns have some limitations. Specifically, they have large numbers of inputs-outputs (I/Os) which is not scalable, and do not support data-buffering. We aim to improve BCGEN’s dataflow communication model by reducing the number of I/Os. Hence, they will be scalable and include data buffering capabilities between logic stages which is typical for data-streaming applications.