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Operating system abstractions of hardware accelerators on field-programmable gate arrays

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Thesis type
(Thesis) M.A.Sc.
Date created
Author: Ismail, Aws
Traditionally, one of the main functions of the Operating System (OS) is to abstract the programming model from the low level details of the speci c HW platform resources. However, in an FPGA-based SoC with HW accelerators, even with an OS layer, there is no uni ed HW/SW framework that provides: 1) transparency to the SW designer at the application level; and 2) an interface and OS support for easy HW accelerator integration by the HW designer at the platform level. This thesis presents a Front-end USEr framework, called FUSE, that introduces a set of policies and mechanisms for HW accelerator abstraction. We illustrate FUSE as an API for an embedded Linux OS with POSIX threads on Xilinx's MicroBlaze on a Virtex5 FPGA. For three di erent applications and HW accelerators, we achieve performance speedups ranging from 5.8-9.0x.
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Supervisor or Senior Supervisor
Thesis advisor: Shannon, Lesley
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