Soc prototyping and validating during DSM CMOS technology transfer

This report lays out the importance in different technology used from one wafer process foundation to another. Depending on the process technologies they use, processed devices can have varying performance and characteristics. The HSPICE BSIM3 model is used to analyze IV characteristics of NIPMOS transistors based on both FAB1 and FAB2 technology files. Sub-threshold current has also been simulated. Simple five stage inverters as well as ring oscillator with 100nm length and 200nm width transistors are created to simulate and analyze the performance variations. The analysis consists of delay associated with parasitic capacitance parameters from both foundries. Lastly, a simple model, consisting of series of inverters and resistors, is created to simulate effect of power distribution.