Analysis of substrate noise suppression and latchup prevention in 90nm CMOS technology with 2-D simulation

As a consequence of increasing system operating frequencies and reduced device spacing, substrate noise interference is becoming an ever growing problem. Substrate noise degrades the performance and the functionality of analog and digital circuits. In this thesis, physical principles, characteristics and effectiveness of substrate noise isolation techniques are investigated through two dimensional device simulations based on 90 nm CMOS technology. Analyses of the research focus on high frequency noise up to 100 GHz for close proximity noise propagation. To evaluate noise suppression techniques with quantified standards, S21 parameters are extracted for structural analysis. The effectiveness of different noise suppression techniques are explained and compared, with suggestions addressing proper design and application. Effects of the noise suppression configurations on latchup events are also demonstrated through simulation, which further verifies the applicability of proposed solutions under latchup prone conditions.