Skip to main content

Analysis of single-ended 6T SRAM cell in 90nm CMOS technology and implementation of charge recycling memory architecture

Resource type
Thesis type
(Thesis) M.A.Sc.
Date created
As CMOS process technology advances into deep sub-micron era, static leakage power becomes an important design consideration for engineers. Static random access memory (SRAM) occupies over 50% of total transistor counts in a SoC design, and therefore it is essential to minimize its stand-by current for low power applications. This thesis presents a single ended input/output 6T SRAM cell with write-assist (WAcell) feature in 90nm CMOS technology. Without the bit-lines being constantly precharged, the static power of a WAcell is reduced by 6.3X using leakage-biased bit-line technique. The minimized subthreshold currents can be collected to build charge pools and used as a power source to help charge bit lines. The proposed write-assist SRAM memory has reduced overall active power by 42% and standby power by 75% compared to traditional SRAM memory. A complete memory design using WAcell with decoders, write driver and sense amplifiers is also presented in this thesis.
Copyright statement
Copyright is held by the author.
The author has not granted permission for the file to be printed nor for the text to be copied and pasted. If you would like a printable copy of this thesis, please contact
Scholarly level
Member of collection
Download file Size
etd3025.pdf 29.41 MB

Views & downloads - as of June 2023

Views: 40
Downloads: 16