Skip to main content

Physical layout design and analysis of charge recycling SRAM system with write-assist feature in 90nm CMOS technology

Resource type
Thesis type
(Thesis) M.A.Sc.
Date created
2007
Authors/Contributors
Abstract
Transistor leakage power will account for more than 50% of total chip power as process technology advances into submicron regime. To counter increasing subthreshold leakage current in traditional SRAM, a new 6T single-ended input/output WA-SRAM is analyzed. WA-SRAM employs a charge-recycling technique to reduce static power of large size SRAM. This thesis describes the physical layout implementation of a 2KByte WA-SRAM system in 90nm CMOS technology and the analysis of the effectiveness of a charge recycling technique. The WA-SRAM exhibits 75% less leakage power per bit than standard SRAM cells in standby mode. Most dynamic operations of WA-SRAM exhibit less active power consumption than standard SRAM with a few exceptions. The exceptions are highly dependent on the type of operation of the previous cycle. The WA-SRAM has shown the potential of supplying the recycled charges to other circuits as a power source when cache size exceeds 9Kbytes.
Document
Copyright statement
Copyright is held by the author.
Permissions
The author has not granted permission for the file to be printed nor for the text to be copied and pasted. If you would like a printable copy of this thesis, please contact summit-permissions@sfu.ca.
Scholarly level
Language
English
Member of collection
Download file Size
etd2972.pdf 40.54 MB

Views & downloads - as of June 2023

Views: 0
Downloads: 2