Resource type
Thesis type
(Thesis) M.Sc.
Date created
2024-08-15
Authors/Contributors
Author: Anil Kumar, Anagha Molakalmur
Abstract
The slowdown of Moore's law and Dennard scaling has emphasized the importance of domain-specific architectures. These architectures improve compute performance by leveraging architectural specialization to achieve efficiency and performance gains to handle specific tasks and applications, that traditional scaling could no longer provide. Current domain-specific architectures (DSAs) work with static data structures, only supporting in-place updates (updates that don't require data structure modifications). As DSAs target real-world applications, supporting mutable and dynamically resizable data structures becomes necessary. DSAs lack a synchronization facility, so they cannot support dynamic data structures and are forced to use address-based atomics or batch updates on the host. Both approaches introduce prohibitive performance penalties, requiring large lock caches. Range-blocks (RBlox) develops a hardware synchronization facility for DSAs to support dynamic data structures, using key ranges to capture synchronization boundaries, tapping into the inherent parallelism of the data structure layout. We make two novel contributions, along with hardware implementation: i) Range locks are symbolic, compactly representing mutexes on multiple nested objects. Thus, any insert requires a single range lock, and a small on-chip table suffices (2kb) compared to large caches (256kb) for address-based locks. ii) Ranges explicitly represent regions of interest, instantly achieving mutual exclusion. On a 128-tile dataflow DSA, we improve performance by 15×, reduce DRAM bandwidth by 4×, save 70% of on-chip traffic, and require 6.6% of on-chip energy (we demonstrate scalability up to 256 tiles).
Document
Extent
46 pages.
Identifier
etd23288
Copyright statement
Copyright is held by the author(s).
Supervisor or Senior Supervisor
Thesis advisor: Shriraman, Arrvindh
Language
English
Member of collection
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