Exploiting TLB sharing to improve performance in server CPUs

Simultaneous Multithreading (SMT) is a fundamental feature that improves the performance of modern CPUs via thread-level parallelism. SMT allows the CPU to issue instructions from different threads on the same core by sharing CPU resources among threads, therefore improving performance when these resources are under-utilized. However, SMT threads suffer from negative inter-thread interference where one thread's resource use degrades the performance of other threads, which affects the Quality of Service (QoS) in server CPUs. In this thesis, we observe that cooperative threads, i.e., threads from the same process that share a virtual address space, interfere positively, where one thread's performance can benefit from another thread sharing CPU resources. To exploit this observation, we propose simple architectural changes that enable effective sharing of the Translation Lookaside Buffer (TLB) by cooperative threads. The Operating System (OS) needs to notify the hardware whether the currently mapped threads are cooperative. Our architecture will take advantage of running cooperative threads by sharing the TLB instead of partitioning it to improve performance.