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Improving Performance of Three-Phase MAF-PLL Under Asymmetrical DC-Offset Condition

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Author: Amini, Jalal
Synchronization is a critical aspect of integrating renewable energy sources and inverter-based power plants into the electrical grid. Phase-Locked Loops (PLLs) are widely used for this purpose, providing rapid and accurate phase and frequency estimation. In PLLs, the Moving Average Filter (MAF) is commonly employed to extract the fundamental grid voltage component, particularly in the presence of harmonic distortions. Traditional PLLs with a full-cycle time-window MAF perform well in grids with sinusoidal voltage waveforms and DC offsets. However, this approach sacrifices the speed of dynamic response due to the extended time window. In this paper, we introduce a novel approach to address this trade-off. Our method involves reducing the MAF’s time window to one cycle by incorporating a delay operator, effectively reducing model complexity and runtime by 50%. Through comprehensive simulations and experimental scenarios, we demonstrate the practical advantages of the proposed method. Comparison of the proposed approach is provided with existing algorithms in the literature, which illustrate its effectiveness in terms of mitigating PLL oscillations in the presence of DC offsets and other non-ideal grid conditions while achieving a 50% improvement in the execution speed. Therefore, the contribution of this paper is in the field of grid synchronization by providing a balanced solution that enhances dynamic response without compromising DC-offset rejection. The proposed method can improve the stability and efficiency of grid-connected systems involving renewable energy sources and inverter-based power plants.
DOI: 10.1109/ACCESS.2023.3322430
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IEEE Access
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Improving Performance of Three-Phase MAF-PLL Under Asymmetrical DC-Offset Condition
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