Application-specific designs can use hardware, such as Field Programmable Gate Array(FPGA)s, to have complete freedom. This includes defining data types as opposed to usingthe predefined standard data types supported in software that are restricted by the architectureof the target processor. Moreover FPGAs are extremely popular for computationallyintensive applications that use either integer or fixed-point calculations and have a limitedpower budget. Static Random-Access Memory (SRAM)-based FPGAs also have the potentialfor a high level of reliability by leveraging their ability to be reconfigured at runtime.In this thesis, we have selected two case studies for hardware acceleration: 1) a biomedicalimaging system for our investigations on precision and reliability Fourier Domain OpticalCoherence Tomography (FD-OCT), and 2) and a Synthetic Aperture Radar (SAR) systemfor our investigations on reliability.Fixed-point arithmetic provides faster and smaller hardware implementations for DigitalSignal Processing (DSP) applications at the expense of accuracy. Especially, when a FastFourier Transform (FFT)-Inverse Fast Fourier Transform (IFFT) pair are required as partof the calculation, the error introduced into the calculations can be significant. This errormostly affects the phase information of the processing signal. Thus, for phase sensitiveapplications, such as FD-OCT, this degradation is unacceptable. For example, a 32-bitfixed-point implementation of FD-OCT on an FPGA could result in a 78% of error comparedto double precision calculations. In order to retain the accuracy of both SAR andFD-OCT implementations, we numerically analyzed the algorithm versus fixed-point, integerand floating point numbers and introduced the adaptability of integer transforms forsuch applications, specially FD-OCT. Then, by using our custom designed Integer SplitRadix Fast Fourier Transform (Int-SRFFT) and Integer Radix-22 FFT, we decreased themaximum peak error from 78% to less than 1 percent. Moreover, a mathematical reliabilitymodel has been developed for an on-board SAR processor that informs the appropriatetechniques for increasing the reliability of the final SAR processor implementation. Variousupset mitigation strategies are introduced and two customized strategies are proposed forthis specific application. The proposed methods are based on truth vectoring and scheduledscrubbing that achieved an increase of robustness of the system by the factor of 3.8 and 4.8respectively.
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Thesis advisor: Shannon, Lesley
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