Asymmetric Coherent Configurable Caches for PolyBlaze Multicore Processor

Modern computing systems gain performance by several means such as increased parallelism through using Chip-level Multiprocessor (CMP) systems. Symmetric Multiprocessor (SMP) systems use uniform processing cores to form a CMP in which all cores are identical in every aspect. Conversely, Asymmetric Multiprocessor (AMP) systems consist of processing cores with variable configurations such as different cache configurations, co-processors, and cache sizes. AMP systems coupled with such smart scheduling algorithms can improve resource utilization while maintaining overall system performance because real-time profiling in a computing system using light-weight hardware profilers can help smart scheduling algorithms make meaningful decisions. In other words, the vision into an application’s behavior helps in the decision making process on how to allocate available resources for different applications without penalizing the performance by putting too much overhead on the system. Currently, there is no AMP research framework available that allows us to look into asymmetry in processing systems. In this thesis, we present an extension on PolyBlaze framework for asymmetric coherent Level-1 (L1) caches. Our implementation in this work includes other arbiter and prefetching units as well. We measure data cache read miss rates and application run-times for select benchmarks from SPEC CPU2006 executed in a Linux environment on top of a variety of cache configurations. In the scope of this work, we manually assign applications to cores to take advantage of AMP configurations. Our results show that in a AMP system, different applications can benefit from various configurations to complete their work faster using less resources.