TERRAE: A framework for adaptive hardware concurrent systems

Resource type
Thesis type
(Thesis) M.A.Sc.
Date created
2012-10-03
Authors/Contributors
Abstract
Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs) is a technology that enables the development of embedded systems with hot swappable logic on the FPGA fabric. The advantage is that hardware logic can be swapped in and out “on-the-fly” while the rest of the system is operational. Since DPR is relatively new, tool support is still evolving. This thesis introduces new FPGA architectural tools and Linux OS modifications that aid in supporting DPR on FPGAs for concurrent control. It shows that control systems benefit from hardware concurrency, meaning that by moving the control intelligence into hardware, the negative effects inherent to threads and their scheduler are minimized. This leaves software with the role of a high-level administrator rather than an executor, thereby eliminating unnecessary bottlenecks. The tools described in this thesis enable the hardware engineer to develop DPR-FPGA systems more effectively for rapid control system development. Furthermore, the introduced Adaptive Hardware Concurrent System (AHCS) architecture illustrates how a designer can take operating systems to a new level of concurrency resulting in true deterministic concurrency implemented on DPR-enabled hardware platforms.
Document
Identifier
etd7498
Copyright statement
Copyright is held by the author.
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The author granted permission for the file to be printed and for the text to be copied and pasted.
Scholarly level
Supervisor or Senior Supervisor
Thesis advisor: Gruver, William A.
Thesis advisor: Hobson, Richard
Member of collection
Attachment Size
etd7498_VLesau.pdf 3.9 MB