High-level abstractions for FPGA-based control systems to improve usability and reduce design time

Field Programmable Gate Array (FPGA)-based control systems offer advantages over processor-based control systems in terms of reliability, concurrent processing, and higher throughput. Although FPGAs are generally reconfigured between applications, Dynamic Partial Reconfiguration (DPR) allows multiple Hardware Modules (HMs) to time-share a pre-defined portion of the programmable fabric while the remainder of the fabric stays active. The advantages of DPR include partial updateability of the programmable fabric, which can reduce a design’s footprint, cost, device count, and power dissipation. The goal of this Thesis is to extend the advantages of FPGA-based control systems by raising the level of abstraction to facilitate their designs. This is achieved in two ways: firstly, a new CAD tool is developed to extend software automation; secondly, a framework is created that incorporates the use of DPR. The framework abstracts the intricate low-level design details and leverages software engineering concepts to facilitate the development of FPGA-based control applications. HMs within the framework are encapsulated with light-weight, customizable wrappers that provide high-level communication functionality.