Development of an area-efficient and low-power five-transistor SRAM for low-power SoC

Resource type
Thesis type
(Thesis) M.A.Sc.
Date created
The purpose of this thesis is to introduce a new low-power, reliable and high-performance five-transistor (5T) SRAM in 65nm CMOS technology, which can be used for cache memory in processors and low-power portable devices. An area reduction of ~13% compared to a conventional 6T cell is possible. A biasing ground line is charged by channel leakage current from memory cells in standby, and is used to pre-charge a single bit-line and bias the negative supply voltage of each memory cell to suppress standby leakage power. A major standby power reduction is gained compared to conventional 5T and 6T designs, and up to ~30% compared to previous low-power 6T designs. Read, write, and standby performance and reliability issues are discussed and compared with conventional and low-power 6T SRAM designs.
Copyright statement
Copyright is held by the author.
The author has not granted permission for the file to be printed nor for the text to be copied and pasted. If you would like a printable copy of this thesis, please contact
Scholarly level
Supervisor or Senior Supervisor
Thesis advisor: Hobson, Richard F.
Thesis advisor: Syrzycki, Marek
Member of collection
Attachment Size
etd6047_HJarollahi.pdf 3.98 MB