FPGA technology mapping for fracturable look-up table minimization

Resource type
Thesis type
(Thesis) M.A.Sc.
Date created
2011-08-11
Authors/Contributors
Abstract
Modern commercial Field-Programmable Gate Array (FPGA) architectures contain lookup-tables (LUTs) that can be “fractured” into two smaller LUTs. The potential to pack two LUTs into a space that could accommodate only one LUT in traditional architectures complicates FPGA technology mapping’s resource minimization objective. Previous works introduced edge recovery techniques and the concept of LUT balancing, both of which produce mappings that pack into fewer fracturable LUTs. We combine these two ideas and evaluate their effectiveness for one commercial and four academic FPGA architectures, all of which contain fracturable LUTs. When combined, edge-recovery and LUT balancing yield a 9.0% to 16.1% reduction in fracturable LUT use, depending on the architecture. We also present a modified technology mapping algorithm called MO-Map that reduces fracturable LUT utilization by 9.7% to 17.2%.
Document
Identifier
etd6712
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Copyright is held by the author.
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The author granted permission for the file to be printed and for the text to be copied and pasted.
Scholarly level
Supervisor or Senior Supervisor
Thesis advisor: Shannon, Lesley
Member of collection
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etd6712_DDickin.pdf 3.8 MB

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