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Self-aligned polysilicon gate metal-oxide-semiconductor field effect transistor for large area electronics

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(Thesis) M.A.Sc.
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Currently, the established large area technology is amorphous silicon where device performance is sacrificed for uniformity and low cost of fabrication. In this research, we investigate crystalline silicon technology for large area application that requires high performance devices. For example, digital X-ray tomosynthesis is one application where amorphous silicon technology cannot satisfy the requirements of low noise and real-time operation. In this work, self-aligned polysilicon gate MOSFET was developed. To achieve this goal, gate dielectric materials and gate materials were studied and a self-aligned MOSFET was developed. A mask set was designed in Cadence and devices were fabricated in the SFU IMMR fabrication facility. Characterization of the devices by C-V and I-V measurements were carried out. The results indicate that an inhouse fabrication of uniform self-aligned polysilicon gate MOSFET based electronics is possible if oxide quality can be maintained.
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