Design of Interface Circuits for Capacitive Sensing Applications

Author: 
Date created: 
2014-08-08
Identifier: 
etd8568
Keywords: 
Interface circuit
Capacitive sensors
Wide dynamic range
Low power consumption
Abstract: 

This thesis focuses on the design of integrated readout circuits for differential capacitive sensing applications. Such circuits are needed especially for interfacing with microsensors where capacitive transduction is predominantly used. The result of this research is the development of common framework for interface circuitries suitable for different sensing applications. These interface circuits were designed and fabricated in standard Complementary Metal-Oxide-Semiconductor (CMOS) processes and can be integrated into the design of various sensing systems. The proposed circuits in this work are characterized by high dynamic range, low power consumption, and adjustable sensing range. Such circuits promote easy-to-use user interfaces while having a low cost. Three different circuit designs were proposed and form the highlights of this thesis. The first interface circuit is a novel realization of a synchronous demodulation technique. The main advantage of the proposed circuit compared to state-of-the-art is that it has a high sensing dynamic range of 112dB and is capable of measuring capacitance as small as 30 aF with a total power consumption of 8mW. Low power consumption is one of the most important design criteria for portable sensing systems besides accuracy and precision. Following this requirement, low power consumption is the main criterion in the second circuit proposed in this work. This circuit uses a switch-based capacitance-to-voltage converter that is designed and fabricated in 0.35μm CMOS technology. This circuit had a low power consumption of 600μW. Its simple structure offers area and power advantages over the more complex circuits. In addition, its ratiometric sensing feature provides an adjustable sensing range which can be tuned for different applications. This circuit can detect capacitances as small as 230 aF in 1pF range of capacitance. To reduce the effect of parasitics on the circuit performance and improve the linearity, the design of the second circuit was enhanced. By using an additional block and an analog divider, the sensitivity of the circuit to parasitics was significantly reduced. On the other hand, a time based output allowed for the elimination of the analog buffers. The fabricated circuit consumed a total power of only 720μW and was fabricated in 0.35μm CMOS technology. Another advantage of this circuit over the previous designs is that the pulse-width output signal of this circuit can be more easily digitized. The proposed circuits in this thesis have been tested with different types of sensors including humidity, motion, and variable MEMS capacitors. For all of them also, the measurement results are found to be in good agreement with the analytic and simulation results. These circuits can be used as standalone chips or can be integrated into the design of larger sensing systems.

Document type: 
Thesis
Rights: 
Copyright remains with the author. The author granted permission for the file to be printed, but not for the text to be copied and pasted.
File(s): 
Supervisor(s): 
Behraad Bahreyni
Department: 
Applied Sciences: School of Mechatronic Systems Engineering
Thesis type: 
(Thesis) Ph.D.
Statistics: